I am a formal verification engineer at Arm, where I work on next-generation IPs with a focus on formal sign-off, property checking, scalable FPV environments, and complex hardware validation across compute and control-heavy designs. My background spans formal verification and product engineering roles at Arm, Intel, and CommScope, along with earlier research in wireless systems and 5G C-RAN at IIT Bhilai, IIT Hyderabad, and IIT Kanpur.
Applying formal verification on next-generation IP blocks for formal sign-off, with an emphasis on scalable verification strategy and high-confidence hardware validation.
Owned formal property verification for next-generation memory controller and hardware reset sequencer blocks, developed an end-to-end FPV environment for scheduler verification, and supported a 10+ engineer formal verification team.
Added Multi RU support to the O-RAN compliant fronthaul of CommScope's ONECELL product and contributed to wireless infrastructure software in a production environment.
Worked on dynamic functional split selection in 5G C-RAN systems under traffic and fronthaul constraints, leading to a publication at IEEE NetSoft.
Designed and simulated a MIMO antenna system using HFSS, and evaluated envelope correlation and related performance metrics using MATLAB.
Owned and executed formal property verification for Intel's next-generation memory controller IP, while helping scale verification across a broader team and delivery pipeline.
Formally verified deadlock and livelock scenarios together with key functional requirements for a next-generation SoC reset sequence controller.
Added multi-RU support to the O-RAN compliant fronthaul of CommScope's ONECELL product.
Proposed a traffic-aware system that dynamically changes split options to keep a 5G C-RAN deployment as centralized as possible under fronthaul and traffic constraints.
CGPA: 9.19/10